The testing of a printed circuit board, populated with components to form a circuit pack which performs one or more electronic functions, is generally accomplished by the use of automatic testing equipment. A typical automatic testing machine comprises a plurality of electronic circuits, each coupled to a particular one of a plurality of test points on the bottom of the circuit board, each connected to one or more component leads. Signals from the testing machine are launched into selected test points on the circuit board, causing the circuit pack to produce signals in response thereto. The signals produced by the circuit pack are then received by the testing machine from other test points on the circuit board. By monitoring the response of the circuit pack to the signals launched therein, the automatic testing machine can verify the operation of the circuit pack.
In practice, the electronic circuits of the testing machine are coupled to the selected test points on the bottom surface of the circuit board under test via a strip line board. Typically, the strip line board takes the form of a substrate (e.g., glass epoxy) whose upper and lower major surfaces are metallized. On the upper major surface of the substrate is a first and second family of conductive areas or nodes. Each of the nodes of the first family is connected to the automatic testing machine. The nodes of the second family are spatially arranged the same as the selected test points on the undersurface of the circuit board which are to be connected to the automatic testing machine. Upstanding pins or other suitable means are provided to connect each node of the second family to a corresponding test point on the undersurface of the circuit board.
A plurality of conductive paths are provided on the upper major surface on the strip line board to connect each node of the first family to a separate one of the nodes of the second family. Which of the nodes of the second family is connected to a particular one of the nodes of the first family is not important. Each node of the second family, which is connected to an individual circuit of the testing machine, can be connected to any one of the nodes of the first family. This is because each of the individual circuits of the testing machine can be assigned arbitrarily to a particular one of the nodes of the second family.
The process of routing or establishing the location of the conductive paths on the upper major surface of the strip line board has been a time consuming procedure. Present day routing techniques rely on a variety of heuristics, none of which typically provides a complete solution to the routing problem Often, significant manual effort is required to complete the routing of the conductive paths on the strip line board. A different strip line board is usually required to test each different type of circuit pack because the spatial arrangement of the test points thereon is unique to the type of circuit pack being tested. Therefore, it is extremely useful to be able to route strip line boards in a rapid, efficient manner.
To make the task of routing easier, present day strip line boards are often comprised of two or more individual layers laminated together. Each layer has a plurality of parallel, spaced apart conductive metal strips or paths thereon perpendicular to the conductive paths on each adjacent layer. Through-plated holes (vias) are provided in each layer to connect one or more of the conductive paths thereon to a path on an adjacent layer to establish the desired route of the paths between vias. The grid-like arrangement of the conductive paths on a laminanted strip line board is often referred to as a "Manhattan" geometry because of the analogy to intersecting city streets and avenues. Laminated strip line boards are expensive and time consuming to route.
One solution to the problem of routing conductive paths between each of two families of conductive nodes on a circuit board has been proposed by V. D. Agrawal of AT&T Bell Laboratories, in his paper "Electrostatic Analog for Finding Nonintersecting Paths", Students Journal, The Institute of Electronics and Telecommunication Engineers (India) Vol. 20, No. 1 (1979) at pages 3-7. Agrawal employs a computer to simulate an electrostatic force field on the circuit board between a preselected node in a first family (which is assigned a positive potential) and the boundaries of the board (which are attributed a ground potential). Any obstructions on the board such as screw holes are also attributed a ground potential. The electric field lines within the simulated electrostatic force field, which emanate from the preselected node and terminate at one of the boundaries, are then plotted. The shortest route between the preselected node in the first family, and any one of the nodes in the second family can be represented by the highest potential electric field line passing therebetween.
Once a conductive path is established between the preselected node in the first family and a node in the second family, another node in the first family is preselected. Then, the above-described process of locating the path between the preselected node and one of the nodes in the second family is repeated. After a path has been routed between each node in the first family and a separate one of the nodes in the second family, then the routing the problem has been solved.
Agrawal's technique of routing conductive paths on the circuit board requires that the nodes of the first family be preselected in some fashion. The order in which the nodes of the first family are preselected is important. It is possible that by preselecting one node before another, the resultant conductive paths obtained using Agrawal's routing technique may actually cross. The crossing of conductive paths on the strip line board cannot be tolerated since any crossing paths will produce an undesirable short circuit and impair the testing of a circuit pack.
Accordingly, there is a need for a technique for automatically routing conductive paths between each of two families of nodes on a substrate in a rapid and efficient manner.